The present disclosure relates to technology for non-volatile storage.
Advancements in technology have allowed memory devices to increasingly store more data. For example, NAND memory cards can store more data now than ever before. With this comes a need to transfer data in and out of the memory devices at an ever faster rate. However, challenges arise with faster data transfers. In some cases, those challenges are due to meeting timing specifications at a memory device interface.
Timing specification may be provided by industry specifications. The Open NAND Flash Interface Specification, Revision 3.2 (Jun. 12, 2103), which is published by the Open NAND Flash Interface (ONFI) Working Group, is one such example. Such specifications may define pinouts, pad assignments, ball assignments, etc. The pinouts may define, for example, which pin is to be used for a read enable (RE), which pins are to be used for data I/O etc. Likewise, the pad assignments may define pad location, spacing, and usage (e.g., which pad is RE). Note that specifications for other technologies such as NOR may use terms such as output enable (OE) instead of read enable.
Specifications may also define timing parameters for reading data from the memory device for different modes such as single data rate (SDR), double data rate (DDR), quad data rate (QDR), etc. One example timing parameter is the latency between when RE is asserted by the host and data is available from the memory chip on its output pins (or pads). One challenge in meeting latency is that data transfer rates continue to increase. For example, the ONFI 3.2 standard mentioned above extends a non-volatile DDR2 (NV-DDR2) interface from 400 MB/s to 533 MB/s.
As data transfer rates continue to increase, it is becoming more difficult to meet specified timing parameters, such as read latency.